ASIC Performance Architect & Modeling (University Grad)

Meta; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Silicon Engineering organization seeking an ASIC Engineer focused on performance architecture and modeling. You will define performance modeling strategies, develop cycle-accurate C++ models, and explore microarchitectural trade-offs for Meta's infrastructure ASICs.

Collaboration with architecture, RTL, and software teams is essential. You will build and calibrate workloads for ML training and inference, mentor engineers, and drive long-term modeling toolchains and automation.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.
• Master's or PhD in CS/CE/EE preferred.
• Proficiency in C++ and Python for simulation and automation.
• Experience in ASIC performance modeling and pre-silicon simulation for custom silicon.
• Experience with data center, AI accelerator, or HPC workloads on custom silicon.
• Experience with cycle-accurate or transaction-level models using C++/SystemC.
• Familiarity with SystemVerilog/VHDL and simulation environments.

Responsibilities

• Define and drive architectural performance analysis and modeling for custom ASICs.
• Develop and maintain C++ models of AI chip IPs and subsystems for exploration and software development.
• Develop workloads and kernels for ML training and inference.
• Establish performance analysis methodologies, benchmarks, and bottleneck identification.
• Collaborate with architecture, RTL, and physical design teams to translate requirements into specs.
• Lead cross-functional technical reviews and communicate results to leadership.
• Define long-term performance modeling roadmaps and tooling investments.

Skills

C++

Python

SystemC

ASIC performance modeling

Pre-silicon simulation

CUDA

Education

Bachelor's degree in CS/CE/EE or equivalent

Master's or PhD in CS/CE/EE (preferred)

Tools

SystemVerilog

Job description

Meta's Silicon Engineering organization seeking an ASIC Engineer focused on performance architecture and modeling. You will define performance modeling strategies, develop cycle-accurate C++ models, and explore microarchitectural trade-offs for Meta's infrastructure ASICs.

Collaboration with architecture, RTL, and software teams is essential. You will build and calibrate workloads for ML training and inference, mentor engineers, and drive long-term modeling toolchains and automation.