Senior ASIC Performance Architect & Modeling Engineer

Meta; Cheyenne (WY); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

In this role, you will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture,

Qualifications

• Bachelor's degree or equivalent in CS/CE or related field.
• 8+ years in ASIC design or silicon engineering.
• 5+ years in ASIC performance modeling or pre-silicon simulation.
• Proficiency in C++ and Python for models and tools.
• Experience with SystemC and cycle-accurate models.

Responsibilities

• Define and own the performance modeling strategy for custom infrastructure ASICs.
• Drive microarchitectural exploration and trade-off analysis.
• Develop and validate pre-silicon models predicting post-silicon behavior.
• Collaborate with architecture, RTL, and physical design teams.
• Lead reviews and communicate results to leadership.
• Mentor engineers in modeling techniques.

Skills

C++

Python

SystemC

Performance modeling

Microarchitectural analysis

Pre-silicon simulation

Mentoring

Automation frameworks

Root-cause analysis

Education

Bachelor's degree in Computer Science/Engineering or related field

Equivalent practical experience

Tools

SystemVerilog

VHDL

SystemC

Simulation environments

Job description

Meta's Silicon Engineering organization is building custom silicon solutions powering Meta's AI and data center workloads. As an ASIC Engineer specializing in performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure.

In this role, you will establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with architecture,