Senior ASIC Performance Architect & Modeling Engineer

Meta; Sunnyvale (CA); Hybrid; USD 190,000 - 240,000; Full time

Job summary

Meta's Silicon Engineering organization in Sunnyvale, CA is seeking an ASIC Engineer specializing in architecture, performance and modeling. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.

Collaborate with architecture, RTL, and software teams to translate performance goals into implementable microarchitectural specifications, develop C++ models of AI IPs, and create workloads for ML

Qualifications

• Experience in pre-silicon modeling and performance analysis.
• Strong software development skills in C++.
• Ability to collaborate with architecture, RTL, and software teams.

Responsibilities

• Drive microarchitectural exploration across compute, memory, interconnect, and I/O.
• Define and own performance modeling strategy for custom infrastructure ASICs.
• Develop and maintain C++ models of AI chip IPs and subsystems.
• Develop workloads and kernels for ML training and inference.
• Collaborate with RTL, design, and physical teams to meet performance targets.

Skills

C++ modeling

Performance analysis

Microarchitecture

Workload development

Collaboration

Tools

Cycle-accurate simulators

Emulation tools

Job description

Meta's Silicon Engineering organization in Sunnyvale, CA is seeking an ASIC Engineer specializing in architecture, performance and modeling. You will define and drive architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs for Meta's infrastructure.

Collaborate with architecture, RTL, and software teams to translate performance goals into implementable microarchitectural specifications, develop C++ models of AI IPs, and create workloads for ML