Senior ASIC Packaging Architect — FC-BGA & MCM Expert

K2 Space Corporation; Seattle (WA); On-site; USD 200,000 - 280,000; Full time

Benefits offered by this job

Equity in company

Comprehensive benefits package

Job summary

K2 Space Corporation in Seattle seeks a Principal ASIC Package Design Engineer to lead FC-BGA and MCM packaging for high-performance mixed-signal and digital SoCs, from architecture through production ramp.

You will set standards, drive trade studies on PI/SI, thermal management, and cooperate with silicon, RF and systems teams to optimize die floorplans and package interfaces, ensuring first-pass success for high-pin-count, high-speed ASICs.

Qualifications

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies, SI/PI fundamentals at package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Manage relationships with external packaging vendors, substrate suppliers, and OSATs, including vendor qualification, capability assessment, contract negotiation, and performance/quality score carding to ensure roadmap and volume commitments are met.
• Drive material selection, substrate technology choices, and assembly process optimization.

Job description

K2 Space Corporation in Seattle seeks a Principal ASIC Package Design Engineer to lead FC-BGA and MCM packaging for high-performance mixed-signal and digital SoCs, from architecture through production ramp.

You will set standards, drive trade studies on PI/SI, thermal management, and cooperate with silicon, RF and systems teams to optimize die floorplans and package interfaces, ensuring first-pass success for high-pin-count, high-speed ASICs.