Senior ASIC Package Design Engineer - Space-Grade FC-BGA

K2 Space Corporation; Los Angeles (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Paid time off

Medical/dental/vision coverage

Life insurance

Paid parental leave

Job summary

K2 Space Corporation is seeking a Senior ASIC Package Design Engineer to implement advanced FC‑BGA and MCM package architectures for high‑performance SoCs. You will work end‑to‑end from architecture through vendor engagement and ramp, collaborating with silicon, RF, and systems teams to ensure first‑pass success.

Responsibilities include defining substrate stack‑ups, trade studies across PI/SI/thermal, and driving standards for package design.

Qualifications

• Bachelor’s degree in Packaging, Mechanical or Electrical Engineering or related field.
• 5+ years of ASIC package design experience with FC‑BGA,

Responsibilities

• Define ASIC package architecture for FC‑BGA and MCM solutions.
• Lead package‑level trade studies across PI, SI, thermal and manufacturability.
• Establish package design standards and best practices.
• Drive FC‑BGA package design for high‑pin‑count ASICs with high‑speed SerDes.
• Collaborate with silicon, RF and systems teams to co‑optimize die floorplans.
• Support package‑level SI/PI strategy and PDN design.
• Lead thermal architecture and mechanical interfaces to system cooling.
• Manage relationships with OSATs and substrate vendors.
• Drive material selection and assembly process optimization.

Skills

FC‑BGA expertise

Si/PI tools

OSAT collaboration

Thermal management

High-pin-count ASICs

Education

Bachelor’s degree in Packaging/Mechanical/Electrical Eng

Tools

SIWave

HFSS

ADS

Job description

K2 Space Corporation is seeking a Senior ASIC Package Design Engineer to implement advanced FC‑BGA and MCM package architectures for high‑performance SoCs. You will work end‑to‑end from architecture through vendor engagement and ramp, collaborating with silicon, RF, and systems teams to ensure first‑pass success.

Responsibilities include defining substrate stack‑ups, trade studies across PI/SI/thermal, and driving standards for package design.