Senior ASIC Package SI/PI Engineer for AI/HPC

OpenAI; San Francisco (CA); On-site; USD 266,000 - 445,000; Full time

Job summary

OpenAI is seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for AI/HPC silicon and package design. You will own SI/PI architecture for high-speed interconnects and work with multi-disciplinary teams from feasibility through production.

The role focuses on 200G/400G SerDes, memory interfaces, 2.5D/3D packaging, and PDN optimization, requiring hands-on EM simulation and practical design guidance.

Qualifications

• 5+ years in signal integrity, power integrity, high-speed interconnect design.
• Strong fundamentals in transmission, impedance, loss, and PDN.
• Hands-on with SI/PI tools listed above and package layout environments.

Responsibilities

• Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility to production.
• Develop and optimize high-speed channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet interfaces.
• Model package, interposer and substrate with 2D/3D EM solvers; define stack-ups and layouts.
• Translate simulation results into actionable package requirements for interposers and substrates.
• Collaborate with ASIC, package, PCB, system, mechanical, thermal, and validation teams.

Skills

SI/PI engineering

High-speed SerDes

Electromagnetic modeling

Cross-functional collaboration

Package design awareness

Education

B.S. in Electrical Engineering

Tools

Synopsys HSPICE

HFSS-PI

Cadence Clarity

Sigrity PowerSI

VNA

Job description

OpenAI is seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for AI/HPC silicon and package design. You will own SI/PI architecture for high-speed interconnects and work with multi-disciplinary teams from feasibility through production.

The role focuses on 200G/400G SerDes, memory interfaces, 2.5D/3D packaging, and PDN optimization, requiring hands-on EM simulation and practical design guidance.