Senior ASIC Lead Neural Recording and Tapeout

Investigo; San Diego (CA); On-site; USD 180,000 - 220,000; Full time

Job summary

Investigo is seeking an experienced ASIC/SoC engineer to own the chip's technical delivery for a neurotechnology project in San Diego. You will be the internal technical authority, ensuring partner work meets the specification and can be defended.

You will decide go/no-go at milestones: architecture reviews, pre-tapeout, and post-silicon disposition, coordinating with the design partner and internal teams to drive successful tapeouts.

Qualifications

• BS/MS in Electrical Engineering with silicon design focus.
• 5+ years in ASIC/SoC design and development.
• Experience on a full ASIC cycle from concept to tapeout.
• Ability to review schematics and simulations critically.

Responsibilities

• Write and maintain versioned ASIC specifications as truth source.
• Lead block, top-level, and pre-tapeout reviews with critique.
• Review SPICE/Cadence simulations, DRC/LVS, and DFT plans.
• Track design risks and drive closure across channels.
• Lead root-cause analysis for test artifacts and silicon bugs.
• Own ECOs and update risk/FMEA for next-gen chips.

Skills

ASIC/SoC design

Analog/mixed-signal design

SPICE/Cadence review

External partner management

Design reviews

Education

B.S./M.S. in Electrical Engineering

Tools

Cadence

Job description

Investigo is seeking an experienced ASIC/SoC engineer to own the chip's technical delivery for a neurotechnology project in San Diego. You will be the internal technical authority, ensuring partner work meets the specification and can be defended.

You will decide go/no-go at milestones: architecture reviews, pre-tapeout, and post-silicon disposition, coordinating with the design partner and internal teams to drive successful tapeouts.