ASIC Technical Lead

Investigo; San Diego (CA); In loco; USD 180.000 - 220.000; Tempo pieno

Descrizione del lavoro

Investigo is seeking an experienced ASIC/SoC engineer to own the chip's technical delivery for a neurotechnology project in San Diego. You will be the internal technical authority, ensuring partner work meets the specification and can be defended.

You will decide go/no-go at milestones: architecture reviews, pre-tapeout, and post-silicon disposition, coordinating with the design partner and internal teams to drive successful tapeouts.

Competenze

• BS/MS in Electrical Engineering with silicon design focus.
• 5+ years in ASIC/SoC design and development.
• Experience on a full ASIC cycle from concept to tapeout.
• Ability to review schematics and simulations critically.

Mansioni

• Write and maintain versioned ASIC specifications as truth source.
• Lead block, top-level, and pre-tapeout reviews with critique.
• Review SPICE/Cadence simulations, DRC/LVS, and DFT plans.
• Track design risks and drive closure across channels.
• Lead root-cause analysis for test artifacts and silicon bugs.
• Own ECOs and update risk/FMEA for next-gen chips.

Conoscenze

ASIC/SoC design

Analog/mixed-signal design

SPICE/Cadence review

External partner management

Design reviews

Formazione

B.S./M.S. in Electrical Engineering

Strumenti

Cadence

Descrizione del lavoro

A neurotechnology company is developing a neural recording ASIC with a high channel count, working with an external IC design house. We are looking for an experienced engineer to own the chip’s technical delivery.

The design partner handles design, simulation, test and fabrication. You will be the internal technical authority who makes sure their work is correct, meets the spec and can be defended. You will decide whether the program moves forward at each major milestone: architecture review, pre-tapeout sign-off and post-silicon disposition.

Key Information

• Contract: Full-time, permanent
• Salary: USD 180,000 – 220,000 per year

Key Responsibilities

• Requirements & specification: Write and maintain the versioned, traceable ASIC specification. It is the single source of truth between the company and the design partner.
• Design & architecture reviews: Lead block-level, top-level and pre-tapeout reviews. Assess schematics, netlists and simulation results yourself rather than relying on summaries.
• Simulation & sign-off: Review SPICE/Cadence simulations, DRC/LVS and DFT plans. Own the tapeout readiness checklist and make the go/no-go decision.
• Risk management: Track design-level risks and see them through to closure. These include process corners, matching, the noise budget and the power budget across all channels.
• First-silicon bring-up: Work with the test and integration team. When results are out of spec, lead the root-cause analysis to tell apart a test artifact, a marginal corner and a real silicon bug.
• Respin leadership: If a respin is needed, lead the design review of the fix and the re-verification plan.
• Sustaining & roadmap: Own engineering change orders and update risk/FMEA files from field and test data. Write the specification for next-generation chips.

Candidate Profile

Must-haves

• B.S. or M.S. in Electrical Engineering (or equivalent), with a focus on silicon design
• 5+ years of experience in ASIC/SoC design and development
• At least one full ASIC development cycle, from concept to silicon (tapeout)
• Strong background in analog or mixed-signal IC design or verification, and confident reviewing and critiquing other engineers’ schematics and simulations
• Working knowledge of SPICE/Cadence simulation review, DRC/LVS and DFT
• Experience managing an external design partner, foundry or fab, and writing specs that keep the partner’s work aligned with what the program needs

Nice-to-haves

• Several successful tapeouts
• Experience in a regulated medical device environment (design controls, DHF, 510(k)/PMA)