Senior ASIC Tech Lead — Neural Recording Chip

Synchron; San Diego (CA); On-site; USD 180,000 - 220,000; Full time

Benefits offered by this job

Subsidized medical and dental保险

401k

Unlimited PTO

Flexible Spending Account

Commuter benefits

Job summary

Synchron seeks a Senior Electrical Engineer, ASIC Technical Lead, to own chip delivery and be the internal technical authority. You will guard specifications, gate partner decisions, and ensure design integrity across tapeout cycles.

You bring extensive ASIC/SoC experience, a track record of silicon delivery, and the ability to shepherd complex, high-channel-count neural recording silicon projects. This role demands leadership and rigorous verification.

Qualifications

• 5+ years of experience in ASIC/SoC design and development.
• At least one full ASIC development cycle from concept to silicon.
• Ability to author and maintain versioned, traceable requirements.
• Experience working with external design partners and foundries.

Responsibilities

• Author and maintain the versioned ASIC requirements and specs.
• Lead design and architecture reviews at each gate with the partner.
• Review SPICE/Cadence simulations, DRC/LVS, and DF T plans; own tapeout readiness.
• Track design-level risks across process corners, matching, noise and power budgets.
• Lead first-silicon bring-up with root-cause analysis for issues.
• If needed, lead the respin review and verification plan.
• Own sustaining changes and roadmap for future chips.

Skills

ASIC/SoC design

Analog/mixed-signal

Schematic review

External partner liaison

DFT concepts

Education

B.S./M.S. in Electrical Engineering

Tools

Cadence SPICE

Cadence tools

Job description

Synchron seeks a Senior Electrical Engineer, ASIC Technical Lead, to own chip delivery and be the internal technical authority. You will guard specifications, gate partner decisions, and ensure design integrity across tapeout cycles.

You bring extensive ASIC/SoC experience, a track record of silicon delivery, and the ability to shepherd complex, high-channel-count neural recording silicon projects. This role demands leadership and rigorous verification.