Senior ASIC Implementation Engineer – UPF, Timing Lead

Amazon Inc.; Sunnyvale, Northern (CA, KY); Hybrid; USD 213,000 - 288,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

RSUs

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in Sunnyvale is seeking an experienced ASIC implementation engineer to shape power-aware chip design for LEO satellite communications. You will collaborate with ASIC teams to define UPF-based power intents and drive RTL and netlist validation.

You will establish flow for both logic and physical synthesis across multiple CMOS nodes, lead timing sign-off, coordinate with RFIC and P&R teams, and ensure DFM criteria are met through IR/EM checks.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8+ years of experience in ASIC implementation (synthesis, STA, P&R for deep sub-micron nodes).
• Experience leading the methodology and scripts for physical synthesis.
• Proven track record taping out chips that reached high-volume production.
• Familiar with chips with multiple power islands and power gating.

Responsibilities

• Develop the chip power intent using UPF with the ASIC design team.
• Validate UPF at RTL and netlist level with standard tools.
• Set up logic and physical synthesis flow for multiple technology nodes.
• Develop implementation methodologies, including AI-assisted flows.
• Coordinate with ASIC, DFT, RFIC and P&R teams for integration and timing.
• Check RTL for clean synthesis, perform STA and LEC on netlists.
• Ensure top-level integration with RFIC and P&R teams and connectivity checks.
• Lead timing sign-off for the post P&R database and verify IR/EM DFMs.

Skills

ASIC implementation

Synthesis/STA/DFM

P&R for sub-micron nodes

Power management UPF

Education

Bachelor's degree in Electrical Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

UPF tooling

Industry standard EDA tools

Job description

Amazon Kuiper Manufacturing Enterprises LLC in Sunnyvale is seeking an experienced ASIC implementation engineer to shape power-aware chip design for LEO satellite communications. You will collaborate with ASIC teams to define UPF-based power intents and drive RTL and netlist validation.

You will establish flow for both logic and physical synthesis across multiple CMOS nodes, lead timing sign-off, coordinate with RFIC and P&R teams, and ensure DFM criteria are met through IR/EM checks.