Lead ASIC Implementation Engineer – Low-Power UPF Expert

Amazon; San Diego (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer in San Diego to drive power intent using UPF and lead physical design flows. You will collaborate with RTL, DFT, RFIC, and P&R teams to deliver robust, low-power silicon for LEO satellite modems and gateways.

The role requires 8+ years in ASIC implementation, a strong track record in tape-outs, and expertise in multi-power island designs.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8+ years of experience in ASIC implementation and deep sub-micron nodes (16nm+).
• Experience leading or developing methodology and scripts for physical synthesis.
• Proven track record taping out chips for high volume production.
• Familiar with multiple power islands and power gating.

Responsibilities

• Develop chip power intent using UPF with the ASIC team.
• Validate UPF at RTL and netlist level using industry tools.
• Set up flow for logic and physical synthesis across nodes.
• Develop implementation methodologies including AI-assisted flows.
• Create timing constraints with ASIC/DFT teams and verify RTL design.
• Ensure clean synthesis, perform STA and LEC on nets.
• Coordinate RFIC integration and top-level shared blocks.
• Oversee P&R handoffs and ensure timely execution by P&R teams.
• Lead timing sign-off for post P&R database and verify DFM criteria.

Skills

ASIC implementation

Synthesis

STA

P&R

UPF flow

Education

Bachelor's degree in Electrical Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

UPF

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer in San Diego to drive power intent using UPF and lead physical design flows. You will collaborate with RTL, DFT, RFIC, and P&R teams to deliver robust, low-power silicon for LEO satellite modems and gateways.

The role requires 8+ years in ASIC implementation, a strong track record in tape-outs, and expertise in multi-power island designs.