Senior ASIC Physical Design Engineer — AI-Driven Flows

Amazon Inc.; San Diego (CA); On-site; USD 154,000 - 215,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior physical design engineer to advance ASIC implementation for high-performance, sub-micron nodes in support of the Low Earth Orbit satellite initiative. You will collaborate with RTL/logic, architecture, and RF/Analog teams to drive design closure and implement robust power-aware solutions.

The role requires 5+ years in ASIC flows, strong synthesis/STA experience, and a track record in multi-team environments.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of ASIC implementation experience including synthesis, STA, and DFT/P&R for sub-micron nodes.
• Master's degree in Electrical or Communications Engineering preferred.
• Experience evaluating 3rd party IP and RF/Analog/Mixed signal blocks integration with digital top flows.
• Experience with power-performance-area tradeoffs and physical design closure.

Responsibilities

• Work with RTL/logic designers to drive architectural feasibility studies and explore tradeoffs for physical design closure.
• Drive IO/Core block physical implementation through synthesis, floor planning, pin planning, place-and-route, power/clock distribution, timing closure, ECO and sign-off.
• Develop physical design methodologies including AI flow integrations.
• Evaluate 3rd party IP and provide recommendations.
• Collaborate with RTL/Architecture teams and other physical design engineers in a multi-site environment.

Skills

ASIC implementation

Physical design

Synthesis/STA

Power analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Communications Engineering

Tools

UPF flow

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior physical design engineer to advance ASIC implementation for high-performance, sub-micron nodes in support of the Low Earth Orbit satellite initiative. You will collaborate with RTL/logic, architecture, and RF/Analog teams to drive design closure and implement robust power-aware solutions.

The role requires 5+ years in ASIC flows, strong synthesis/STA experience, and a track record in multi-team environments.