Senior ASIC Implementation Engineer – UPF & P&R Lead

Amazon; Sunnyvale (CA); Sur place; USD 213 000 - 288 000; Plein temps

Avantages offerts par ce poste

Health insurance

401(k) matching

Paid time off

Parental leave

Résumé du poste

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer to define and implement digital SOCs for LEO satellite communications. You will collaborate with ASIC design, DFT, RFIC, and P&R teams to deliver robust, low-power designs across multiple technology nodes, validating UPF, and leading timing sign-off.

The role emphasizes driving flow, leveraging AI-enabled methodologies, and ensuring high-quality PPA through every stage from RTL to mask.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 8+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
• Experience leading or solely developing the methodology and scripts for physical synthesis.
• Proven track record in taping out chips that have gone in to high volume production.
• Familiar with implementing chips that have multiple power islands and power gating.

Responsabilités

• As the implementation engineer you will work with the ASIC design team to develop the chip power intent using UPF.
• As the implementation lead you will work with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools.
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Develop implementation methodologies while embracing AI flow.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to ensure top-level integration of analog blocks is correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure smooth handoff of netlists and timely execution of P&R responsibilities.
• Participate in flow reviews of all blocks with P&R team to achieve best PPA for all blocks.
• Lead timing sign-off for the post P&R database.
• Ensure the chip meets the required DFM criteria by verifying IR/EM results.

Connaissances

ASIC implementation

Power-aware design

STA/Timing analysis

Team leadership

Formation

Bachelor's in Electrical Engineering

Master's/PhD in Electrical/Communications Engineering

Outils

Synthesis tools

P&R tools

STA/LEC tools

Description du poste

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer to define and implement digital SOCs for LEO satellite communications. You will collaborate with ASIC design, DFT, RFIC, and P&R teams to deliver robust, low-power designs across multiple technology nodes, validating UPF, and leading timing sign-off.

The role emphasizes driving flow, leveraging AI-enabled methodologies, and ensuring high-quality PPA through every stage from RTL to mask.