Lead ASIC Implementation Engineer – Low-Power SoCs

Amazon; Sunnyvale (CA); On-site; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer to define and implement SOCs for high-speed satellite communications. You will collaborate with ASIC, DFT, RFIC, and P&R teams to drive UPF-based power intent, RTL/netlist validation, and timing sign-off across multiple technology nodes.

The role emphasizes leading physical design flow, developing robust methodologies, and ensuring design-for-manufacturability with strong focus on power integrity

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 5+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
• Experience leading or solely developing the methodology and scripts for physical synthesis.
• Proven track record in taping out chips that have gone in to high volume production.
• Familiar with implementing chips that have multiple power islands and power gating.

Responsibilities

• As the implementation engineer you will work with the ASIC design team to develop the chip power intent using UPF.
• As the implementation lead you will work with the ASIC design team to validate UPF at RTL and netlist level using industry standard tools.
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Develop implementation methodologies while embracing AI flow.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to ensure proper top-level integration of analog blocks by construction, including connectivity checks.
• Work with P&R teams to ensure smooth hand off of netlists and timely execution of P&R responsibilities.
• Participate in flow reviews of all blocks with P&R to achieve best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure chip meets required DFM criteria by verifying IR/EM results.

Skills

ASIC implementation

Synthesis

STA

P&R

UPF flow

Power integrity

Education

Bachelor's degree in Electrical Engineering

Tools

P&R tools

RTL validation

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced ASIC implementation engineer to define and implement SOCs for high-speed satellite communications. You will collaborate with ASIC, DFT, RFIC, and P&R teams to drive UPF-based power intent, RTL/netlist validation, and timing sign-off across multiple technology nodes.

The role emphasizes leading physical design flow, developing robust methodologies, and ensuring design-for-manufacturability with strong focus on power integrity