Senior ASIC Frontend Engineer - RTL & SystemVerilog

Upscale AI, Inc.; Northern (KY); Hybrid; USD 212,000 - 246,000; Full time

Job summary

Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets.

You will collaborate with architecture, verification, emulation, and physical design teams to validate test plans, closures, and DFT integration in a fast-paced startup environment. Ideal candidates have SystemVerilog expertise, 3+ years of ASIC logic design, and strong teamwork capabilities to help drive

Qualifications

• BE or MS in EE, CE, CS.
• 3+ years of technical engineering experience.
• 3+ years of logic design on complex ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of logic design principles, clock domain crossing, synthesis and timing closure.
• Strong communication and teamwork in cross-functional teams.
• Thrives in a fast-paced startup environment.],
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Responsibilities

• As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.
• Responsible for the logic design/RTL entry that meets the power, performance, area targets.
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization
• Work with the design for test team to integrate DFT logic
• Work independently, communicate effectively and collaborate with cross functional teams

Skills

SystemVerilog

Clock domain crossing

Synthesis & timing closure

Team collaboration

Startup environment

Communication

Education

BE or MS in EE, CE, CS

Tools

LINT

CDC

RDC

Job description

Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets.

You will collaborate with architecture, verification, emulation, and physical design teams to validate test plans, closures, and DFT integration in a fast-paced startup environment. Ideal candidates have SystemVerilog expertise, 3+ years of ASIC logic design, and strong teamwork capabilities to help drive