Principal ASIC RTL Engineer

Upscale AI, Inc.; Northern (KY); Hybrid; USD 250,000 - 265,000; Full time

Job summary

Upscale AI, Inc. is hiring for an ASIC Design engineer to shape next-gen AI infrastructure. You will work with architecture and define micro-architecture, delivering RTL that meets power, performance, and area targets.

Join a fast-paced startup with a culture of ownership and technical rigor. Expect collaboration with verification, physical design, and test teams, and opportunities to influence high-impact AI workloads.

Qualifications

• BE or MS in EE, CE, CS.
• 5+ years of related engineering experience.
• 5+ years in logic design on complex ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of clock domain crossing and timing closure.
• Strong communication and teamwork in fast-paced teams.
• Able to thrive in a startup environment.

Responsibilities

• Define and document micro-architecture for next-gen ASIC designs.
• Deliver RTL logic design meeting power, performance, area targets.
• Coordinate with verification/emulation to ensure test coverage.
• Collaborate with physical design for timing closure and area optimization.
• Integrate DFT logic with design-for-test teams.
• Work independently and collaborate across cross-functional teams.

Skills

SystemVerilog

Logic design

ASIC design

Team collaboration

Startup environment

Education

Bachelor's or Master's in EE/CE/CS

Tools

LINT

CDC

RDC

Job description

Upscale AI, Inc. is hiring for an ASIC Design engineer to shape next-gen AI infrastructure. You will work with architecture and define micro-architecture, delivering RTL that meets power, performance, and area targets.

Join a fast-paced startup with a culture of ownership and technical rigor. Expect collaboration with verification, physical design, and test teams, and opportunities to influence high-impact AI workloads.