IC - Frontend - Senior Staff Engineer

Upscale AI, Inc.; Northern (KY); Hybrid; USD 212,000 - 246,000; Full time

Job summary

Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets.

You will collaborate with architecture, verification, emulation, and physical design teams to validate test plans, closures, and DFT integration in a fast-paced startup environment. Ideal candidates have SystemVerilog expertise, 3+ years of ASIC logic design, and strong teamwork capabilities to help drive

Qualifications

• BE or MS in EE, CE, CS.
• 3+ years of technical engineering experience.
• 3+ years of logic design on complex ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of logic design principles, clock domain crossing, synthesis and timing closure.
• Strong communication and teamwork in cross-functional teams.
• Thrives in a fast-paced startup environment.],
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Responsibilities

• As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.
• Responsible for the logic design/RTL entry that meets the power, performance, area targets.
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization
• Work with the design for test team to integrate DFT logic
• Work independently, communicate effectively and collaborate with cross functional teams

Skills

SystemVerilog

Clock domain crossing

Synthesis & timing closure

Team collaboration

Startup environment

Communication

Education

BE or MS in EE, CE, CS

Tools

LINT

CDC

RDC

Job description

Why join Upscale AI

Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale AI is where you can produce meaningful work at the frontier—and operate at a high standard.

Job Responsibilities

• As a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs.
• Responsible for the logic design/RTL entry that meets the power, performance, area targets.
• Collaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure
• Work closely with the physical design team on timing closure and area optimization
• Work with the design for test team to integrate DFT logic
• Work independently, communicate effectively and collaborate with cross functional teams

Requirements

• BE or MS in EE, CE, CS
• 3+ years of related technical engineering experience.
• 3+ years of industry experience in logic design on complex ASICs
• Experience with SystemVerilog for logic design
• Understanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure
• Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Able to thrive or lead in a fast-paced startup environment.

Preferred

• 10+ years of relevant industry experience with a proven track record of successful tapeouts
• Scripting proficiency using Python, Perl etc.
• Experience with front end design tools like LINT, CDC, RDC
• Exposure to silicon bring-up
• Analyzing timing, area, power reports and ability to drive design fixes
• Knowledge of verification principles and coverage and ability to debug complex test cases
• Basic understanding of formal verification
• Past work experience on high performance, low latency networking ASICs is a big plus
• Growth mindset and enthusiasm to learn and grow in a fast paced environment

$212,000 - $246,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale AI is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.