Senior ASIC Front‑End Design Engineer for AI Inference

Anysilicon; Sunnyvale (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Tensordyne, a leading AI system solution company, seeks an experienced ASIC engineer to lead frontend physical design for generative AI inference in Sunnyvale, CA. You will guide optimization, collaborate with backend teams, and drive EDA-driven workflows from synthesis to timing analysis.

The role requires 10+ years in ASIC engineering, strong Cadence/Synopsys experience, and proven frontend/back-end design expertise with clock trees and timing constraints.

Qualifications

• 10+ years hands-on ASIC engineering experience and VLSI/SoC design knowledge.
• Strong experience with Cadence/Synopsys Genus/DC and power analysis.
• Expertise in front-end optimization and timing constraints.

Responsibilities

• Lead ASIC frontend physical design and workflow development for AI inference products.
• Guide frontend design improvements at block and full-chip levels.
• Drive optimization and new frontend design workflows, including synthesis and power analysis.
• Provide guidance for static timing analysis (STA) and timing constraints.
• Collaborate with ASIC teams to improve workflows and EDA needs.
• Contribute to scalable, high-performance systems and tools.

Skills

ASIC engineering

Frontend optimization

STA knowledge

Global teamwork

Problem solving

Education

Bachelor's degree in EE/CE

Master's degree in EE/CE

Tools

Cadence Genus/DC

Synopsys power analysis

Power analysis tools

EDA knowledge

Job description

Tensordyne, a leading AI system solution company, seeks an experienced ASIC engineer to lead frontend physical design for generative AI inference in Sunnyvale, CA. You will guide optimization, collaborate with backend teams, and drive EDA-driven workflows from synthesis to timing analysis.

The role requires 10+ years in ASIC engineering, strong Cadence/Synopsys experience, and proven frontend/back-end design expertise with clock trees and timing constraints.