Senior ASIC Architect for Generative AI Hardware

Tensordyne; Sunnyvale (CA); Hybrid; USD 150,000 - 200,000; Full time

Benefits offered by this job

Competitive pay

Comprehensive benefits

Flexibility

Recognition programs

Job summary

Tensordyne, based in Sunnyvale, CA, is looking for an experienced engineer to lead ASIC architecture for generative AI processors. In this role, you will manage the design and implementation of cutting-edge silicon solutions essential for AI inference. Candidates should have over 15 years of hands-on experience in silicon design and a strong understanding of generative AI algorithms.

Your work will involve coordinating with various engineering teams, ensuring that product specifications meet performance and power efficiency standards. This is a unique opportunity to influence the future of AI technology.

Qualifications

• 15+ years of silicon design engineering and architectural planning experience.
• Deep expertise in generative AI algorithms and related hardware mapping.
• Experience with performance modeling and debugging.

Responsibilities

• Lead architectural planning and design for AI processors.
• Prepare detailed design specifications and milestones.
• Evaluate new silicon IP technologies and enhance chip design process.

Skills

Silicon design engineering

High performance compute (HPC) processors

Verilog programming

C/C++ programming

Performance analysis and optimization

Education

MS or PhD in Electrical Engineering, Computer Engineering or related

Tools

RTL verification tools

EDA tools

SystemC or TLM

Scripting languages (Python, Perl)

Job description

Tensordyne, based in Sunnyvale, CA, is looking for an experienced engineer to lead ASIC architecture for generative AI processors. In this role, you will manage the design and implementation of cutting-edge silicon solutions essential for AI inference. Candidates should have over 15 years of hands-on experience in silicon design and a strong understanding of generative AI algorithms.

Your work will involve coordinating with various engineering teams, ensuring that product specifications meet performance and power efficiency standards. This is a unique opportunity to influence the future of AI technology.