Senior ASIC Physical Design Engineer

Anysilicon; Sunnyvale (CA); Híbrido; USD 180.000 - 240.000; Jornada completa

Descripción de la vacante

Tensordyne, a leading AI system solution company, seeks an experienced ASIC engineer to lead frontend physical design for generative AI inference in Sunnyvale, CA. You will guide optimization, collaborate with backend teams, and drive EDA-driven workflows from synthesis to timing analysis.

The role requires 10+ years in ASIC engineering, strong Cadence/Synopsys experience, and proven frontend/back-end design expertise with clock trees and timing constraints.

Formación

• 10+ years hands-on ASIC engineering experience and VLSI/SoC design knowledge.
• Strong experience with Cadence/Synopsys Genus/DC and power analysis.
• Expertise in front-end optimization and timing constraints.

Responsabilidades

• Lead ASIC frontend physical design and workflow development for AI inference products.
• Guide frontend design improvements at block and full-chip levels.
• Drive optimization and new frontend design workflows, including synthesis and power analysis.
• Provide guidance for static timing analysis (STA) and timing constraints.
• Collaborate with ASIC teams to improve workflows and EDA needs.
• Contribute to scalable, high-performance systems and tools.

Conocimientos

ASIC engineering

Frontend optimization

STA knowledge

Global teamwork

Problem solving

Educación

Bachelor's degree in EE/CE

Master's degree in EE/CE

Herramientas

Cadence Genus/DC

Synopsys power analysis

Power analysis tools

EDA knowledge

Descripción del empleo

Tensordyne, a leading AI system solution company, specializes in high-performance, low-power generative AI inference systems. With a mission to accelerate multimodal generative AI inference at scale, Tensordyne is at the forefront of innovation in AI technology. The company, headquartered in Sunnyvale, CA, and Munich, Germany, offers a supportive work environment with comprehensive benefits and competitive compensation, aiming to build a healthy and motivated team to drive technological advancements.

Responsibilities:

• Lead ASIC front-end physical design and engineering workflow development for generative AI inference products.
• Guide and assist colleagues in improving frontend physical design at both block and full-chip levels.
• Drive optimization, implementation, and exploration of new frontend physical design workflows, including synthesis, formal checks, and power analysis.
• Provide guidance for static timing analysis (STA) and contribute to the full ASIC chip design process.
• Innovate and improve scalable, reliable, high-performance systems and tools for next-generation products.
• Collaborate closely with ASIC team members to understand and enhance their workflows and EDA needs.

Qualifications:

• 10 years of hands‑on ASIC engineering experience with deep knowledge of VLSI/SoC chip physical design workflows.
• Experience with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, and clock methodology.
• Strong physical design knowledge for front-end optimization using standard EDA tools.
• Experience leading backend design teams with understanding of clock trees, routing, DRC, LVS, and metal fill until artwork release.
• Understanding of STA analysis and constraints for block level and full chip timing analysis.
• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.

Skills:

• Excellent analytical, written, and verbal interpersonal skills.
• Ability to collaborate productively within a global engineering team in a fast‑paced startup environment.
• Strong problem‑solving skills with a focus on designing, debugging, and optimizing EDA solutions.