Senior ASIC Emulation Engineer – Networking SoCs

AMD; Santa Clara (CA); On-site; USD 160,000 - 210,000; Full time

Job summary

AMD is seeking a hands-on MTS ASIC Emulation Engineer to lead emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms. You will define emulation strategy, build scalable environments, enable hardware-software co-verification, and drive functional and performance validation before silicon.

The role spans high-speed Ethernet, PCIe, DMA, RDMA, packet processing, and related workloads, requiring strong debug and leadership to coordinate across architecture,

Qualifications

• Hands-on emulation and verification experience is required.
• Strong RTL, firmware, software debugging skills are essential.
• BS or MS in Electrical/Computer Engineering or Computer Science.

Responsibilities

• Define emulation architecture and bring-up on ZeBu, Veloce, Palladium or equivalents.
• Enable HW-SW co-verification with firmware and software teams; drive regression and validation.
• Validate networking data paths (Ethernet, PCIe, DMA, RDMA) and system performance.
• Lead workload enablement, debugging, and provide technical leadership across teams.

Skills

C/C++

Python

RTL debugging

Leadership

Education

EE/CE/CS degree

Tools

ZeBu

Veloce

Palladium

Job description

AMD is seeking a hands-on MTS ASIC Emulation Engineer to lead emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms. You will define emulation strategy, build scalable environments, enable hardware-software co-verification, and drive functional and performance validation before silicon.

The role spans high-speed Ethernet, PCIe, DMA, RDMA, packet processing, and related workloads, requiring strong debug and leadership to coordinate across architecture,