ASIC Emulation Engineer: HW/SW Bring-Up & Verification

Amazon; Sunnyvale (CA); On-site; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an Emulation Engineer to define the emulation bring-up environment for ASIC and system-level emulation of next-generation modems. You will write scripts, develop bare metal code, debug test benches, and work with RTL, verification, and silicon validation teams in a high-visibility role.

The role requires 5+ years in SOC emulation, proficiency with Verilog/SystemVerilog/VHDL, and experience on Cadence Palladium or Mentor Veloce.

Qualifications

• Bachelor's degree required in EE or related field.
• 5+ years in SOC emulation and validation.
• Experience with emulation platforms (Cadence Palladium, Mentor Veloce).
• Proficiency in Verilog/SystemVerilog/VHDL and C/C++.
• Scripting in Python, Tcl, or Perl; strong debugging skills.

Responsibilities

• Build and bring-up emulation models for complex SOC designs.
• Develop and maintain emulation environments and methodologies.
• Debug complex hardware issues using emulation platforms.
• Develop and maintain C++ based emulation testbench framework.
• Create and execute verification test plans.
• Interface with RTL, verification, and silicon validation teams.
• Enable software bring-up and root-cause debugging with software teams.
• Optimize emulation performance and resource utilization.
• Document processes, methodologies, and specifications.

Skills

C/C++

Python scripting

Debugging

Firmware development

Verilog/SystemVerilog/VHDL

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Computer Science/Engineering (preferred)

Tools

Cadence Palladium

Mentor Veloce

UVM verification

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking an Emulation Engineer to define the emulation bring-up environment for ASIC and system-level emulation of next-generation modems. You will write scripts, develop bare metal code, debug test benches, and work with RTL, verification, and silicon validation teams in a high-visibility role.

The role requires 5+ years in SOC emulation, proficiency with Verilog/SystemVerilog/VHDL, and experience on Cadence Palladium or Mentor Veloce.