Senior ASIC Emulation Engineer - Lead Silicon Validation

K2 Space; Los Angeles (CA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Paid time off

Medical insurance

Dental insurance

Vision insurance

Paid parental leave

Job summary

K2 Space is seeking a Senior ASIC Emulation Engineer to lead pre-silicon bring-up and optimization. You will work with architecture, RTL design, DV, firmware, and silicon teams to enable high‑fidelity hardware/software co‑development and accelerate verification cycles.

This hands‑on role requires deep experience with Palladium, ZeBu, or Veloce, strong SystemVerilog and scripting skills, and a track record of emulation performance optimization.

Qualifications

• Bachelor's or Master's in EE/CE or related field.
• Extensive experience with emulation in ASIC/SoC development.
• Strong scripting for automation (Python/Perl/TCL).
• Hands-on with major emulation platforms and DV methodologies.

Responsibilities

• Build, integrate, and maintain full-chip and system-level emulation models.
• Define emulation strategy and workflows across the organization.
• Collaborate with RTL, DV, firmware, and design teams for optimization.
• Develop transactors, BFMs, and virtualization interfaces.
• Support system-level testing and end-to-end workloads in emulation.
• Improve verification throughput and DV content adaptation.
• Assist firmware/bootloader teams with HW/SW integration.
• Triage failures, root-cause analysis, and cross-functional debug.
• Automate compile flows and regression management.
• Participate in architecture reviews and emulation best practices.
• Support silicon bring-up and pre/post-silicon validation.
• Coordinate with external IP providers or emulation partners.

Skills

SystemVerilog

RTL design

DV methodologies

Emulation platforms

Python/Perl/TCL

C/C++ testing

Hardware/software interfaces

Education

B.S./M.S. in Electrical Engineering or Computer Engineering

Tools

Palladium

ZeBu

Veloce

Job description

K2 Space is seeking a Senior ASIC Emulation Engineer to lead pre-silicon bring-up and optimization. You will work with architecture, RTL design, DV, firmware, and silicon teams to enable high‑fidelity hardware/software co‑development and accelerate verification cycles.

This hands‑on role requires deep experience with Palladium, ZeBu, or Veloce, strong SystemVerilog and scripting skills, and a track record of emulation performance optimization.