Senior ASIC Emulation Engineer

K2Spacecorporation; United States; On-site; USD 170,000 - 250,000; Full time

Job summary

K2 Space is building the largest and highest-power satellites. We are seeking a Senior ASIC Emulation Engineer to lead bring-up, deployment, and optimization of pre-silicon emulation platforms, working with architecture, RTL, DV, firmware, physical design, and silicon validation teams to accelerate verification cycles.

This hands-on role offers high ownership and the opportunity to shape first-generation silicon and system methodology for a high-performance space mission stack.

Qualifications

• 5+ years in ASIC/SoC development focused on emulation.
• Strong SystemVerilog, DV methods, and RTL flow knowledge.
• Experience with major emulation platforms and model build.
• Proficiency in Python, Perl, TCL for automation.
• Experience with hardware/software interfaces and C/C++ testing.

Responsibilities

• Build, integrate, and maintain full-chip and system-level emulation models.
• Define emulation strategy, workflow, and cross-team collaboration.
• Optimize designs for emulation performance, capacity, and stability.
• Develop transactors, BFMs, and virtualization interfaces.
• Support system-level emulation testing with end-to-end workloads.
• Triage issues, perform root-cause analysis, and drive fixes.
• Improve automation for CI, regression, and compile flows.
• Assist in hardware/software integration during bring-up.

Skills

SystemVerilog

RTL flows

DV methodologies

Python

C/C++ testing

HW/SW interfaces

JTAG

Debug cross-functional

Education

B.S. in Electrical Engineering

M.S. in Electrical Engineering

Tools

Palladium

ZeBu

Veloce

FPGA prototyping

HAPS

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup.

The Role

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high-fidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon and system methodology.

Responsibilities

• Build, integrate, and maintain full-chip, multi-chips and system-level emulationmodels on platforms such as Palladium, ZeBu, or Veloce.
• Define and evolveemulationstrategy, methodology, and workflows across the ASIC organization.
• Work with RTL engineers to compile, map, and optimize designs foremulationperformance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
• Support system-level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end-to-end workloads.
• Accelerate overall verification throughput by helping DV team run targeted and high-value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
• Enable firmware, bootloader, driver, and software teams by providing robustemulationplatforms and assisting in HW/SW integration debug.
• Runemulationworkloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulationbest practices.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
• Manage interactions with external IP providers oremulationpartners when needed.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC development, focused on emulation
• Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
• Hands-on expertise with majoremulationplatforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.
• Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
• Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
• Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice to Have

• Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
• Experience with low-power modes and power-awareemulation.
• Experience with analog/mixed-signal behavioral models inemulationenvironments.
• Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.

Compensation and Benefits:

• Base salary range for this role is $170,000 - $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person".

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.