Senior ASIC Emulation Engineer: Drive Pre-Silicon Innovation

K2Spacecorporation; Seattle (WA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Comprehensive benefits

Paid time off

Equity

Job summary

K2 Space is seeking a Senior ASIC Emulation Engineer to lead bring-up and optimization of pre-silicon emulation platforms. You will collaborate with architecture, RTL, DFT, DV, firmware, and silicon validation teams to enable high-fidelity hardware/software co-development and accelerate verification cycles.

This hands-on role requires ownership, deep technical engagement, and shaping first-generation silicon and system methodology for missions across LEO to deep space.

Qualifications

• 5+ years of experience in ASIC/SoC development, focused on emulation.
• Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
• Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce) including model build, debug and performance optimization.
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.
• Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.

Responsibilities

• Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
• Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
• Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
• Support system-level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end-to-end workloads.
• Accelerate overall verification throughput by helping DV team run targeted and high-value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
• Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
• Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
• Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
• Manage interactions with external IP providers or emulation partners when needed.

Skills

SystemVerilog

DV methodologies

RTL flows

C/C++-based testing

Python scripting

Education

B.S. or M.S. in Electrical Engineering or related field

Tools

Palladium

ZeBu

Veloce

HAPS

Protium

Job description

K2 Space is seeking a Senior ASIC Emulation Engineer to lead bring-up and optimization of pre-silicon emulation platforms. You will collaborate with architecture, RTL, DFT, DV, firmware, and silicon validation teams to enable high-fidelity hardware/software co-development and accelerate verification cycles.

This hands-on role requires ownership, deep technical engagement, and shaping first-generation silicon and system methodology for missions across LEO to deep space.