Senior ASIC Emulation Engineer — Lead Pre-Silicon Validation

Mundi; United States; On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Equity

Medical/dental/vision coverage

Paid parental leave

Time off

Job summary

K2 Space is seeking a Senior ASIC Emulation Engineer to lead bring-up, deployment, and optimization of pre-silicon emulation platforms. You will collaborate with architecture, RTL, DFT, DV, firmware, physical design, and silicon validation teams to enable high-fidelity HW/SW co-development and accelerate verification cycles.

This hands-on role provides ownership to shape first‑generation silicon and system methodology.

Qualifications

• BS or MS in EE/CE or related field.
• 5+ years of ASIC/SoC development experience focusing on emulation.
• Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC lifecycles.
• Hands-on expertise with Palladium, ZeBu, Veloce including model build, debug and optimization.
• Proficiency in Python, Perl, or TCL for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, and C/C++-based system testing.
• Familiarity with APB/AHB/AXI, JTAG, SPI buses/protocols.
• Experience driving cross-functional debug with RTL, DV, firmware, physical design, and validation teams.

Responsibilities

• Build, integrate, and maintain full-chip and multi-chip emulation models on Palladium, ZeBu, or Veloce.
• Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
• Collaborate with RTL engineers to optimize designs for emulation performance, capacity, and stability.
• Develop transactors, BFMs, speed adapters, and virtualization interfaces for diverse use cases.
• Support system-level testing in emulation with end-to-end HW/SW workloads.
• Improve DV throughput by optimizing emulation flows and running high-value tests.
• Enable firmware and software teams by providing robust emulation platforms for HW/SW integration.
• Triage failures, perform root-cause analysis, and coordinate across teams.
• Maintain automation for compile flows, regression management, and CI.

Skills

SystemVerilog

RTL flows

DV methodologies

C/C++ testing

Python scripting

Cross-functional debug

Pre/post-silicon debug

Emulation platforms

Hardware/software co-development

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

Palladium

ZeBu

Veloce

Job description

K2 Space is seeking a Senior ASIC Emulation Engineer to lead bring-up, deployment, and optimization of pre-silicon emulation platforms. You will collaborate with architecture, RTL, DFT, DV, firmware, physical design, and silicon validation teams to enable high-fidelity HW/SW co-development and accelerate verification cycles.

This hands-on role provides ownership to shape first‑generation silicon and system methodology.