Senior ASIC Verification Engineer - Hybrid Role

Anysilicon; Santa Clara (CA); Hybrid; USD 130,000 - 170,000; Full time

Job summary

Palo Alto Networks in Santa Clara, CA is seeking a Design Verification Engineer to join the ASIC team. The role focuses on ensuring ASICs in next-generation firewall products meet high standards for features, performance, and reliability.

You will collaborate across software, architecture, design and verification, plan pre-silicon verification, develop flows for emulation, and automate tasks with Python. A BS in engineering with 5+ years of ASIC verification is required.

Qualifications

• BS in Electrical/Computer Engineering or Computer Science required.
• MSEE preferred.
• Minimum 5 years of ASIC design verification experience.
• Experience bringing ASICs from concept to mass production.

Responsibilities

• Collaborate with software, architecture, design, and verification teams to create pre-silicon verification plans.
• Plan and execute simulation test plans using coverage-driven, constrained-random methodologies.
• Develop flows, methodologies, and infrastructure for emulation.
• Create, run, and debug emulation tests with system architects and ASIC designers.
• Define new tools and methodologies to improve quality and velocity.
• Automate verification tasks using Python for triage, coverage closure, and metrics-driven verification.

Skills

SystemVerilog

UVM

Test plans

Coverage models

Test benches

Debugging

Networking

Cybersecurity

Formal verification

Silicon validation

Python scripting

C/C++

Perl

Unix shell

Education

B.S. in EE/CE/CS

MSEE preferred

Tools

Python

C/C++

Perl

Unix shell

Job description

Palo Alto Networks in Santa Clara, CA is seeking a Design Verification Engineer to join the ASIC team. The role focuses on ensuring ASICs in next-generation firewall products meet high standards for features, performance, and reliability.

You will collaborate across software, architecture, design and verification, plan pre-silicon verification, develop flows for emulation, and automate tasks with Python. A BS in engineering with 5+ years of ASIC verification is required.