Senior ASIC DFT Lead & Architect — Mentor & Testability

Tap Growth ai; California (MD); On-site; USD 180,000 - 280,000; Full time

Job summary

Tap Growth ai is seeking a Lead ASIC DFT Staff Engineer to design and implement testability architectures for next-generation ASICs. You will lead DFT strategy, oversee scan insertion, ATPG, BIST, boundary scan, and collaborate across teams to ensure robust, scalable test flows.

The role requires 12+ years of hands-on ASIC DFT experience and strong leadership; expertise in scripting (Perl/Python/TCL) is a plus and communication skills are essential to mentor juniors and coordinate silicon

Qualifications

• 12+ years hands-on ASIC DFT experience.
• Expertise in scan insertion, ATPG, BIST, boundary scan.
• Proven track record leading complex DFT projects.
• Strong communication and teamwork skills.

Responsibilities

• Architect and implement complex DFT strategies for cutting-edge ASIC designs.
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies.
• Collaborate with cross-functional teams on test planning and execution.
• Review and optimize verification flows for quality and efficiency.
• Mentor junior engineers in best practices and technical skills.
• Support silicon bring-up and debug processes post-fabrication.

Skills

ASIC DFT engineering

ATPG

Boundary scan

Perl

Python

TCL

Leadership

Tools

ATPG tools

DFT verification tools

Job description

Tap Growth ai is seeking a Lead ASIC DFT Staff Engineer to design and implement testability architectures for next-generation ASICs. You will lead DFT strategy, oversee scan insertion, ATPG, BIST, boundary scan, and collaborate across teams to ensure robust, scalable test flows.

The role requires 12+ years of hands-on ASIC DFT experience and strong leadership; expertise in scripting (Perl/Python/TCL) is a plus and communication skills are essential to mentor juniors and coordinate silicon