Lead ASIC DFT Architect — Remote & Flexible

Tap Growth ai; California (MO); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Tap Growth ai in California is seeking a Lead ASIC DFT Staff Engineer to drive testability architecture and implementation for advanced ASICs. You will oversee scan insertion, ATPG, BIST, boundary scan, and verification flows.

You will mentor junior engineers, collaborate with cross-functional teams on test planning, silicon bring-up, and post-fabrication debugging. A seasoned expert with 12+ years in ASIC DFT and strong scripting skills is required.

Qualifications

• 12+ years hands-on experience in ASIC DFT engineering.
• Deep knowledge of scan insertion, ATPG, BIST, boundary scan.
• Proven track record leading complex DFT projects from concept to production.
• Strong communication and teamwork skills.
• Expertise in scripting languages (Perl/Python/TCL) is a plus.

Responsibilities

• Architect and implement complex DFT strategies for cutting-edge ASIC designs.
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies.
• Collaborate with cross-functional teams on test planning and execution.
• Review and optimize verification flows for quality and efficiency.
• Mentor junior engineers in best practices and technical skills.
• Support silicon bring-up and debug processes post-fabrication.

Skills

Scan insertion

ATPG

BIST

Boundary scan

Perl/Python/TCL

Job description

Tap Growth ai in California is seeking a Lead ASIC DFT Staff Engineer to drive testability architecture and implementation for advanced ASICs. You will oversee scan insertion, ATPG, BIST, boundary scan, and verification flows.

You will mentor junior engineers, collaborate with cross-functional teams on test planning, silicon bring-up, and post-fabrication debugging. A seasoned expert with 12+ years in ASIC DFT and strong scripting skills is required.