Lead ASIC DFT Staff Engineer

RAPSYS TECHNOLOGIES PTE LTD; California (MD); On-site; USD 170,000 - 210,000; Full time

Job summary

RAPSYS TECHNOLOGIES PTE LTD is seeking a Lead ASIC DFT Staff Engineer to drive testability strategies for advanced ASIC designs. You will architect and implement DFT solutions, oversee scan insertion, ATPG, BIST, and boundary scan, and collaborate with cross-functional teams to ensure robust verification flows.

You will mentor junior engineers, optimize post-fabrication bring-up, and uphold industry standards for quality and efficiency, while communicating clearly with stakeholders across

Qualifications

• 12+ years hands-on experience in ASIC DFT
• Expertise in scan insertion, ATPG, BIST, boundary scan
• Proven track record leading complex DFT projects
• Strong communication and teamwork skills
• Expertise in scripting languages (Perl/Python/TCL) is a plus

Responsibilities

• Architect and implement complex DFT strategies for cutting-edge ASIC designs
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies
• Collaborate with cross-functional teams on test planning and execution
• Review and optimize verification flows for quality and efficiency
• Mentor junior engineers in best practices and technical skills
• Support silicon bring-up and debug processes post-fabrication

Skills

ASIC DFT

Scan insertion

ATPG

BIST

Boundary scan

Scripting (Perl/Python/TCL)

Mentoring

Communication

Tools

ATPG tools

Scan insertion tools

Job description

Join our innovative team as a Lead ASIC DFT Staff Engineer and drive the design for testability of advanced ASICs. We’re looking for an expert with extensive experience to lead DFT architecture, implementation, and verification, ensuring robust and efficient test solutions that meet industry standards.

What You’ll Do:

• Architect and implement complex DFT strategies for cutting-edge ASIC designs
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies
• Collaborate with cross-functional teams on test planning and execution
• Review and optimize verification flows for quality and efficiency
• Mentor junior engineers in best practices and technical skills
• Support silicon bring-up and debug processes post-fabrication

What We’re Looking For:

• Minimum 12 years’ hands‑on experience in ASIC DFT engineering
• Deep knowledge of scan insertion, ATPG tools, BIST, boundary scan
• Proven track record leading complex DFT projects from concept to production
• Strong communication and teamwork skills
• Expertise in scripting languages (Perl/Python/TCL) is a plus