Lead ASIC DFT Staff Engineer

Tap Growth ai; California (MD); On-site; USD 180,000 - 280,000; Full time

Job summary

Tap Growth ai is seeking a Lead ASIC DFT Staff Engineer to design and implement testability architectures for next-generation ASICs. You will lead DFT strategy, oversee scan insertion, ATPG, BIST, boundary scan, and collaborate across teams to ensure robust, scalable test flows.

The role requires 12+ years of hands-on ASIC DFT experience and strong leadership; expertise in scripting (Perl/Python/TCL) is a plus and communication skills are essential to mentor juniors and coordinate silicon

Qualifications

• 12+ years hands-on ASIC DFT experience.
• Expertise in scan insertion, ATPG, BIST, boundary scan.
• Proven track record leading complex DFT projects.
• Strong communication and teamwork skills.

Responsibilities

• Architect and implement complex DFT strategies for cutting-edge ASIC designs.
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies.
• Collaborate with cross-functional teams on test planning and execution.
• Review and optimize verification flows for quality and efficiency.
• Mentor junior engineers in best practices and technical skills.
• Support silicon bring-up and debug processes post-fabrication.

Skills

ASIC DFT engineering

ATPG

Boundary scan

Perl

Python

TCL

Leadership

Tools

ATPG tools

DFT verification tools

Job description

Join our innovative team as a Lead ASIC DFT Staff Engineer and drive the design for testability of advanced ASICs. We’re looking for an expert with extensive experience to lead DFT architecture, implementation, and verification, ensuring robust and efficient test solutions that meet industry standards.

What You’ll Do:

• Architect and implement complex DFT strategies for cutting-edge ASIC designs
• Oversee scan insertion, ATPG, BIST, boundary scan, and related methodologies
• Collaborate with cross-functional teams on test planning and execution
• Review and optimize verification flows for quality and efficiency
• Mentor junior engineers in best practices and technical skills
• Support silicon bring-up and debug processes post-fabrication

What We’re Looking For:

• Minimum 12 years’ hands‑on experience in ASIC DFT engineering
• Deep knowledge of scan insertion, ATPG tools, BIST, boundary scan
• Proven track record leading complex DFT projects from concept to production
• Strong communication and teamwork skills
• Expertise in scripting languages (Perl/Python/TCL) is a plus