Senior ASIC Designer: Memory Acceleration for AI Workloads

Netpreme; Cambridge (MA); On-site; USD 160,000 - 260,000; Full time

Benefits offered by this job

Relocation assistance

Visa sponsorship

Lunch stipend

Equity grant

Job summary

Netpreme is seeking experienced Senior ASIC Designers to lead RTL design of IPs, subsystems, and SOCs for its silicon roadmap. Bring 5+ years in ASIC/SOC design, Verilog/SystemVerilog, and a track record of design leadership.

You will collaborate across architecture, verification, physical design, firmware, DFT, and post-silicon domains, interface with vendors, and drive designs toward aggressive performance, power and area goals in an early-stage AI/datacenter product.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering.
• 5+ years in ASIC/SOC digital design.
• Strong leadership and cross-functional coordination skills.
• Experience across microarchitecture to tape-out in advanced process technologies.
• RTL coding in Verilog/SystemVerilog; timing & physical design knowledge.

Responsibilities

• RTL design of IPs, subsystems, and SOCs for Netpreme's silicon roadmap.
• Define IP/SOC microarchitecture specifications and design methodologies.
• Lead design reviews and optimize for performance, power, and area.
• Collaborate with architecture, verification, physical design, firmware, DFT, and post-silicon domains.
• Interface with external IP vendors, foundries, and EDA tool providers to resolve blockers.

Skills

ASIC design experience

RTL coding (Verilog/SystemVerilog)

Synthesis

STA/timing closure

Physical design

Verification methodologies

Leadership & communication

Cross-functional coordination

DFT knowledge

Education

Bachelor's or Master's in Electrical/Computer Engineering

PhD (preferred)

Tools

EDA tool suites

Job description

Netpreme is seeking experienced Senior ASIC Designers to lead RTL design of IPs, subsystems, and SOCs for its silicon roadmap. Bring 5+ years in ASIC/SOC design, Verilog/SystemVerilog, and a track record of design leadership.

You will collaborate across architecture, verification, physical design, firmware, DFT, and post-silicon domains, interface with vendors, and drive designs toward aggressive performance, power and area goals in an early-stage AI/datacenter product.