Senior ASIC Engineer

Selby Jennings; New York (NY); On-site; USD 120,000 - 180,000; Full time

Job summary

Selby Jennings is seeking an experienced ASIC Design Engineer to join its Hardware Engineering team in New York. You will architect and implement high‑performance digital designs for latency‑sensitive applications, collaborating with ML researchers, software engineers, and quantitative researchers to optimize silicon.

The role requires 5+ years in ASIC design, strong SystemVerilog/RTL skills, and a deep understanding of computer architecture and ASIC flows.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of ASIC digital design experience.
• Expert-level SystemVerilog and RTL development skills.
• Deep understanding of computer architecture, digital logic design, and ASIC implementation flows.
• Experience designing high-performance pipelines, memory subsystems, networking datapaths, or custom compute engines.
• Proficiency with Linux development environments.
• Experience with Python and/or C++.
• Demonstrated ownership of ASIC blocks through multiple stages of the design lifecycle.

Responsibilities

• Architect, design, and optimize high-performance ASIC blocks for latency-sensitive and throughput-intensive applications.
• Develop RTL in SystemVerilog for complex data processing, networking, and machine learning workloads.
• Partner with ML researchers to accelerate inference and feature extraction pipelines in custom silicon.
• Design and implement compute architectures for machine learning models, including transformer, recommendation, and signal-processing workloads.
• Analyze performance, power, and area tradeoffs throughout the design cycle.
• Collaborate with verification, physical design, and FPGA prototyping teams to ensure successful deployment.
• Investigate emerging hardware architectures, AI acceleration techniques, and EDA methodologies.
• Contribute to internal hardware design tools, automation frameworks, and development infrastructure.
• Drive major design blocks from architecture definition through RTL implementation, timing closure support, tapeout, and silicon bring-up.

Skills

SystemVerilog

RTL development

Linux

Python/C++

Education

BS/MS/PhD in ECE/CE/CS

Job description

A leading quantitative technology firm is seeking an experienced ASIC Design Engineer to join its Hardware Engineering team. The team develops custom hardware solutions that power some of the fastest and most sophisticated real-time computing systems in the world. Engineers work across FPGA and ASIC technologies, building everything from ultra-low-latency data processing pipelines to advanced machine learning acceleration platforms.

As an ASIC Design Engineer, you will architect and implement cutting-edge digital designs that directly impact business-critical systems. You will collaborate closely with hardware engineers, machine learning researchers, software engineers, and quantitative researchers to transform complex algorithms into highly optimized silicon. This is a unique opportunity to work at the intersection of custom hardware, machine learning, and large-scale distributed computing.

Responsibilities

• Architect, design, and optimize high-performance ASIC blocks for latency-sensitive and throughput-intensive applications.
• Develop RTL in SystemVerilog for complex data processing, networking, and machine learning workloads.
• Partner with ML researchers to accelerate inference and feature extraction pipelines in custom silicon.
• Design and implement compute architectures for machine learning models, including transformer, recommendation, and signal-processing workloads.
• Analyze performance, power, and area tradeoffs throughout the design cycle.
• Collaborate with verification, physical design, and FPGA prototyping teams to ensure successful deployment.
• Investigate emerging hardware architectures, AI acceleration techniques, and EDA methodologies.
• Contribute to internal hardware design tools, automation frameworks, and development infrastructure.
• Drive major design blocks from architecture definition through RTL implementation, timing closure support, tapeout, and silicon bring-up.

Required Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of ASIC digital design experience.
• Expert-level SystemVerilog and RTL development skills.
• Deep understanding of computer architecture, digital logic design, and ASIC implementation flows.
• Experience designing high-performance pipelines, memory subsystems, networking datapaths, or custom compute engines.
• Proficiency with Linux development environments.
• Experience with Python and/or C++.
• Demonstrated ownership of ASIC blocks through multiple stages of the design lifecycle.

Preferred Qualifications

• Experience designing machine learning accelerators, AI inference engines, or custom compute architectures.
• Knowledge of transformer architectures, neural network acceleration, quantization, sparsity, or model optimization techniques.
• Background in high-speed networking protocols and low-latency system design.
• Experience with FPGA prototyping and hardware/software co-design.
• Familiarity with synthesis, timing closure, physical design constraints, and performance optimization.
• Experience working with large-scale distributed compute or HPC environments.
• Experience building systems where latency, throughput, and performance are critical design considerations.