Member of Technical Staff, ASIC Design

Netpreme; Cambridge (MA); On-site; USD 160,000 - 260,000; Full time

Benefits offered by this job

Relocation assistance

Visa sponsorship

Lunch stipend

Equity grant

Job summary

Netpreme is seeking experienced Senior ASIC Designers to lead RTL design of IPs, subsystems, and SOCs for its silicon roadmap. Bring 5+ years in ASIC/SOC design, Verilog/SystemVerilog, and a track record of design leadership.

You will collaborate across architecture, verification, physical design, firmware, DFT, and post-silicon domains, interface with vendors, and drive designs toward aggressive performance, power and area goals in an early-stage AI/datacenter product.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering.
• 5+ years in ASIC/SOC digital design.
• Strong leadership and cross-functional coordination skills.
• Experience across microarchitecture to tape-out in advanced process technologies.
• RTL coding in Verilog/SystemVerilog; timing & physical design knowledge.

Responsibilities

• RTL design of IPs, subsystems, and SOCs for Netpreme's silicon roadmap.
• Define IP/SOC microarchitecture specifications and design methodologies.
• Lead design reviews and optimize for performance, power, and area.
• Collaborate with architecture, verification, physical design, firmware, DFT, and post-silicon domains.
• Interface with external IP vendors, foundries, and EDA tool providers to resolve blockers.

Skills

ASIC design experience

RTL coding (Verilog/SystemVerilog)

Synthesis

STA/timing closure

Physical design

Verification methodologies

Leadership & communication

Cross-functional coordination

DFT knowledge

Education

Bachelor's or Master's in Electrical/Computer Engineering

PhD (preferred)

Tools

EDA tool suites

Job description

About The Role

We are seeking experienced Senior ASIC Designers.

About The Role

We are seeking experienced Senior ASIC Designers.

This role demands proven technical expertise in advanced ASIC design flows, and leadership in execution, cross-functional coordination, and final product delivery. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.

This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

Essential Duties & Responsibilities

• As part of the Silicon Design Team, responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.
• Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
• Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
• Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
• Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5+ years of ASIC/SOC digital design experience
• Excellent leadership, communication, team building and stakeholder management skills.
• Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
• Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
• Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
• Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
• Design and tapeout of any advanced silicon device is highly preferred.

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience managing relationships with external design partners, IP vendors, and foundries.
• Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.

Compensation & Benefits

• Competitive salary commensurate with experience including base salary, performance-based bonus, and early stage equity grant
• Comprehensive benefits including health, dental, vision, and life insurance
• Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
• Relocation assistance and visa sponsorship
• Perks include a daily lunch stipend, 401k match, and more
• A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing

The Opportunity

• Impact: We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. The work we do here compounds across state-of-the-art AI models, systems, and real-world applications.
• Timing: Joining now means real ownership of the company and meaningful influence over product direction and execution. You'll work from first principles, move quickly from insight to execution, and see your contributions directly reflected in what we build.
• Culture: You'll work alongside a group of people who care deeply about rigor, clarity, and impact. We value thoughtful disagreement, fast learning, and intellectual fearlessness. This is a place where strong ideas shine, curiosity is encouraged, and growth is a daily practice.