Staff RTL Design Engineer

Oho Group; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Oho Group in the San Francisco Bay Area is seeking a Staff ASIC Design Engineer to lead RTL design and microarchitecture for next-generation AI accelerator SoCs.

The role requires 10+ years of ASIC/SoC design experience with exposure to PCIe, CXL or UCIe, memory systems like HBM, and collaboration across architecture, verification, software and system teams.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Hands-on RTL development and microarchitecture ownership.
• Experience with CPUs/GPUs or AI accelerators is highly desirable.
• Familiarity with PCIe, CXL or UCIe interconnects.
• Knowledge of memory controllers and HBM is a plus.

Responsibilities

• Own RTL design and microarchitecture for AI accelerator SoCs.
• Define and review microarchitectural specs and translate to synthesizable RTL.
• Collaborate with verification, software and system teams across the silicon cycle.
• Work on interconnects, NoCs, and high-performance fabric design.
• Validate designs through tests and performance analysis.

Skills

RTL design

ASIC/SoC design experience

NoCs / interconnects

AI accelerator experience

Memory controllers / HBM

PCIe / CXL / UCIe

Education

BS/MS/PhD in Electrical Engineering / Computer Engineering / Computer Science

Job description

Staff ASIC Design Engineer - San Francisco Bay Area - AI Accelerator Startup

About the Role

A fast-moving startup in the Bay Area are looking for ASIC design engineers with strong experience across IP, architecture and microarchitecture within the AI accelerator space. Offering high ownership from day one and the opportunity to work with a world-class team of industry leaders from the top semiconductor companies, this is an exciting role for someone who wants to be a part of something from an early stage.

Key Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

What We're Looking For

• 10+ years of ASIC/SoC design experience, with substantial hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with technologies such as PCIe, CXL or UCIe.
• Experience working on GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Education

BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field.