SDC Design Engineer

InfoObjects Inc.; San Jose (CA); Presencial; USD 150 000 - 230 000; Tempo integral

Resumo da oferta

InfoObjects Inc. seeks a diligent Design/SDC Engineer with strong timing constraints expertise. You will lead fullchip SDC development, collaborate with Front-end and Back-end teams, and guide timing strategies across design levels for next‑gen networking chips.

Responsibilities include overseeing fullchip timing in multiple modes, mentoring RTL owners, and documenting clocking diagrams. Block level RTL design or IP integration may be involved.

Qualificações

• Bachelor’s or Master’s in Electrical or Computer Engineering with 5+–7+ years of ASIC timing experience.
• Experience with block/full chip SDC development in functional and test modes.
• Proficiency in Static Timing Analysis and with PrimeTime/Tempus.
• Understanding of clocking concepts, async boundaries and timing closure.
• Experience with synthesis tools such as Synopsys DC/DCG/FC and Verilog/SystemVerilog.

Responsabilidades

• Oversee fullchip SDCs and work with physical design/DFT to close timing in multiple modes.
• Option to perform block level RTL design or block/top-level IP integration.
• Develop methodologies to promote block level SDCs to fullchip timing and feed changes back to block level.
• Ensure correctness and quality of SDCs early in the design cycle.

Conhecimentos

Static Timing Analysis

Clocking and async boundaries

Verilog/SystemVerilog programming

SSTA automation scripting

Design for timing closure

Formação académica

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Ferramentas

PrimeTime/Tempus

Synopsys DC/DCG/FC

Cadence Conformal Constraint Designer

Spyglass

Formality/LEC

Descrição da oferta de emprego

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities include:

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
• Understanding of related digital design concepts (eg. clocking and async boundaries)
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

• Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
• Experience with Spyglass CDC and glitch analysis
• Experience using Formal Verification: Synopsys Formality and Cadence LEC.
• Experience with scripting languages such as Python, Perl, or TCL