Senior SDC Design Engineer - Chip Timing & Closure

InfoObjects Inc.; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

InfoObjects Inc. seeks a diligent Design/SDC Engineer with strong timing constraints expertise. You will lead fullchip SDC development, collaborate with Front-end and Back-end teams, and guide timing strategies across design levels for next‑gen networking chips.

Responsibilities include overseeing fullchip timing in multiple modes, mentoring RTL owners, and documenting clocking diagrams. Block level RTL design or IP integration may be involved.

Qualifications

• Bachelor’s or Master’s in Electrical or Computer Engineering with 5+–7+ years of ASIC timing experience.
• Experience with block/full chip SDC development in functional and test modes.
• Proficiency in Static Timing Analysis and with PrimeTime/Tempus.
• Understanding of clocking concepts, async boundaries and timing closure.
• Experience with synthesis tools such as Synopsys DC/DCG/FC and Verilog/SystemVerilog.

Responsibilities

• Oversee fullchip SDCs and work with physical design/DFT to close timing in multiple modes.
• Option to perform block level RTL design or block/top-level IP integration.
• Develop methodologies to promote block level SDCs to fullchip timing and feed changes back to block level.
• Ensure correctness and quality of SDCs early in the design cycle.

Skills

Static Timing Analysis

Clocking and async boundaries

Verilog/SystemVerilog programming

SSTA automation scripting

Design for timing closure

Education

Bachelor’s Degree in Electrical or Computer Engineering

Master’s Degree in Electrical or Computer Engineering

Tools

PrimeTime/Tempus

Synopsys DC/DCG/FC

Cadence Conformal Constraint Designer

Spyglass

Formality/LEC

Job description

InfoObjects Inc. seeks a diligent Design/SDC Engineer with strong timing constraints expertise. You will lead fullchip SDC development, collaborate with Front-end and Back-end teams, and guide timing strategies across design levels for next‑gen networking chips.

Responsibilities include overseeing fullchip timing in multiple modes, mentoring RTL owners, and documenting clocking diagrams. Block level RTL design or IP integration may be involved.