Senior ASIC Design Lead: High-Speed DSP & Mixed-Signal

CesiumAstro, Inc.; Aliso Viejo (CA); On-site; USD 15,000 - 199,000; Full time

Benefits offered by this job

Stock options

Health benefits

Dental coverage

Vision coverage

HSA/FSA

Life insurance

Disability insurance

Retirement plans

Job summary

Jariet Technologies, Inc., a CesiumAstro, Inc. subsidiary, seeks a Principal ASIC Design Engineer to lead next‑gen high‑speed mixed‑signal/DSP chips.

You will own cradle‑to‑grave ASIC development, RTL/Vectors with Verilog/SystemVerilog, and drive integration across analog and digital domains in a fast‑paced environment. The role requires a Master’s in Engineering with 10+ years’ experience, leadership, and strong front‑end/back‑end design flow expertise.

Qualifications

• Cradle-to-grave ASIC development experience.
• Strong RTL design, verification, and timing analysis skills.
• Experience with customer communications and leadership.

Responsibilities

• Lead front-end and back-end design flows from concept to silicon.
• Define architecture for high-speed ASICs and DSP blocks.
• Coordinate verification, bring-up, and lab testing activities.

Skills

ASIC design

Verilog/SystemVerilog

UVM/SPECMAN

RTL verification

DSP integration

High-speed analog

Project management

Education

Master’s in Engineering

Tools

Synthesis

STA flow

Back-end flow

EDA tools

Job description

Jariet Technologies, Inc., a CesiumAstro, Inc. subsidiary, seeks a Principal ASIC Design Engineer to lead next‑gen high‑speed mixed‑signal/DSP chips.

You will own cradle‑to‑grave ASIC development, RTL/Vectors with Verilog/SystemVerilog, and drive integration across analog and digital domains in a fast‑paced environment. The role requires a Master’s in Engineering with 10+ years’ experience, leadership, and strong front‑end/back‑end design flow expertise.