Senior ASIC Verification Engineer — Equity & Impact

Woven; Aliso Viejo (CA); In loco; USD 165.000 - 199.000; Tempo pieno

Vantaggi offerti da questo lavoro

Stock options

Generous benefits package including Hs

Descrizione del lavoro

Jariet Technologies, Inc., a CesiumAstro subsidiary, seeks a principal ASIC functional verification engineer in the United States. You will design and implement verification test benches for high-speed digital SoCs, using SystemVerilog, UVM, and coverage-driven methods to ensure first-pass silicon quality.

The role may involve team leadership and close collaboration with the VLSI design team to plan verification strategies and drive project success.

Competenze

• 10+ years of relevant ASIC verification experience with a BS/EE or CS degree, or 8+ years with MS.
• Proficiency in SystemVerilog/UVM, with strong coverage and assertion skills.
• Excellent written and verbal communication abilities.

Mansioni

• Design and implement verification test benches for system, chip, and block levels.
• Develop verification plans and coverage metrics; use UVM-based methodologies.
• Collaborate with VLSI design team to shape verification strategies.

Conoscenze

SystemVerilog

UVM

Coverage verification

Assertions (SVA/PSL/OVL)

Formazione

BS in CS/EE or related

MS in related field

Strumenti

Cadence IFV

Jasper

Descrizione del lavoro

Jariet Technologies, Inc., a CesiumAstro subsidiary, seeks a principal ASIC functional verification engineer in the United States. You will design and implement verification test benches for high-speed digital SoCs, using SystemVerilog, UVM, and coverage-driven methods to ensure first-pass silicon quality.

The role may involve team leadership and close collaboration with the VLSI design team to plan verification strategies and drive project success.