Principal ASIC Design Engineer - Chip Lead

Cesiumastro; Aliso Viejo (CA); On-site; USD 15,000 - 199,000; Full time

Benefits offered by this job

Stock options

Health benefits (dental, vision)

HSA/FSA programs

Retirement plans

Job summary

CesiumAstro is seeking a Principal ASIC Design Engineer – Chip Lead in its Jariet Technologies group in California. You will drive cradle-to-grave high-speed mixed-signal/DSP chip projects, from architecture through production.

The role demands deep RTL/SystemVerilog expertise, verification using UVM/VMM/SPECMAN, and collaboration with frontend/backend teams to meet demanding performance, power, and timing goals. A Master’s degree and 10+ years' experience are required.

Qualifications

• Master’s in Engineering with 10+ years of experience.
• Experience in IC/ASIC development flow from concept through silicon release.
• System simulation to RTL, verification, synthesis, and backend interfacing.
• High-speed analog block integration into digital logic.
• Ability to analyze specs at architecture/micro-architecture levels.
• Excellent program management and project tracking skills.
• Experience with customer communications and marketing interactions.
• ASIC verification experience using UVM, VMM, OVM or SPECMAN.
• Fluency with Verilog/SystemVerilog; synthesis/STA; low-power design desirable.
• DSP block implementation desirable.

Responsibilities

• Lead cradle-to-grave ASIC/Chip design programs for high-speed mixed-signal DSP.
• Collaborate with frontend/backend teams to move silicon from concept to production.
• Engage with customers and cross-functional teams to define requirements.

Skills

IC/ASIC development flow

RTL design

High-speed DSP

UVM/VMM/SPECMAN verification

Synthesis & STA

Low power design

Project management

Customer communications

Education

Master’s in Engineering

Tools

UVM

VMM

SPECMAN

Job description

Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.

This position is with Jariet Technologies, Inc., a subsidiary of CesiumAstro. Jariet is developing breakthrough technologies to permit digital communications technology to be applied at micro/mm-Wave speeds using standard CMOS processes. Jariet is well positioned to provide ASIC products into emerging markets in multi-antenna beamforming communications systems and wireless infrastructure as well as digital deployments into microwave point-to-point links and radar systems. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team.

We are looking to add a Principal ASIC Design Engineer - Chip Lead for our next generation industry leading high speed mixed signal/DSP projects. We are specifically looking for someone with cradle-to-grave experience who knows all levels of large, high-speed communications chip design. The ideal candidate will have knowledge in all or most of the following areas: digital communications systems, DSP, ASIC microarchitecture, analog IP integration, embedded processors, high level verification, RTL design with multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring up, debug, lab testing, and transitioning a product from first sample through release to volume production.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

• Master’s in Engineering with a minimum of 10 years of experience.
• Experience with the IC/ASIC development flow from concept through production release of silicon.
• Experience in defining and using advanced front-end design flows from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team.
• Experience in high speed analog block integration into digital logic.
• The candidate must have a well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements.
• Excellent program management, people management, and project tracking skills.
• Experience with customer communications and marketing/sales interactions.
• Experience with ASIC verification using random constraint coverage driven verification methodology like UVM, VMM, OVM or SPECMAN.
• Fluency with Verilog and System Verilog, experience with synthesis, formal verification, and STA flow set up. Experience with low power design flows highly desirable.
• Experience in DSP block implementation highly desirable.

$15,000 - $199,000 a year

CesiumAstro considers several factors when extending an offer, including but not limited to, the role and associated responsibilities, a candidate’s work experience, education/training, and key skills. Full-time employment offers include company stock options and a generous benefits package including health, dental, vision, HSA, FSA, life, disability and retirement plans.

CesiumAstro is an Equal Opportunity employer. All qualified applicants will receive consideration for employment without regard torace, color, religion, sex, national origin, disability, protected Veteran Status, or any other characteristic protected by applicable federal, state, or local law.

Please note: CesiumAstro does not accept unsolicited resumes from contract agencies or search firms. Any unsolicited resumes submitted to our website or to CesiumAstro team members will be considered property of CesiumAstro, and we will not be obligated to pay any referral fees.