Senior Analog/Mixed-Signal ASIC Design Lead (Hybrid)

Taara Connect, Inc.; Sunnyvale (CA); Hybrid; USD 258,000 - 294,000; Full time

Job summary

Taara Connect, Inc. is seeking a Principal Analog/Mixed‑Signal ASIC Design Engineer to drive the next generation of co‑integrated electronic and photonic modules.

You will own AMS ASIC blocks, contribute to tape‑out, and work with a small team across design, layout, and test to deliver high‑precision converters and robust analog circuitry. Ideal candidates have 10+ years of experience in analog/mixed‑signal design, tapeouts in modern CMOS/BCD, and a track record of bringing complex ASICs to

Qualifications

• Ph.D. in Electrical Engineering or a related field.
• 10+ years of analog/mixed‑signal circuit design in CMOS.
• Expertise in high‑precision DACs/ADCs, bandgap references, regulators, amplifiers.
• Tapeout experience in BCD tech with silicon bring‑up.
• Experience with AMS design verification, layout, and mixed‑signal sim.
• Hands‑on with multiple ASIC tape‑outs at commercial foundries.
• Experience with DRC, LVS, PI, SI verification.

Responsibilities

• Own ASIC design blocks for co‑integration with photonic ICs.
• Contribute to tape‑out, delivery, and validation of ASIC dies.
• Perform AMS design verification and layout work.
• Collaborate with a small team of ASIC designers, layout, and test engineers.

Skills

AMS design expertise

Tapeout experience

ADC/DAC design

High‑precision circuits

Chip top‑level ownership

DRC/LVS verification

Education

PhD in Electrical Engineering

Tools

Calibre

RTL toolchain

GDS design flow

Job description

Taara Connect, Inc. is seeking a Principal Analog/Mixed‑Signal ASIC Design Engineer to drive the next generation of co‑integrated electronic and photonic modules.

You will own AMS ASIC blocks, contribute to tape‑out, and work with a small team across design, layout, and test to deliver high‑precision converters and robust analog circuitry. Ideal candidates have 10+ years of experience in analog/mixed‑signal design, tapeouts in modern CMOS/BCD, and a track record of bringing complex ASICs to