Senior ASIC Verification Engineer — SoC Testbench Lead

Cesiumastro; Aliso Viejo (CA); On-site; USD 165,000 - 199,000; Full time

Benefits offered by this job

Stock options

Benefits package

Job summary

Jariet Technologies, Inc., a CesiumAstro subsidiary, is seeking a Principal ASIC Functional Verification Engineer to shape verification strategies for high-speed SoCs. You will craft advanced test benches, apply UVM/OVM/VMM, and partner with the VLSI design team to ensure robust coverage and correctness in digital communications silicon.

Ideal candidates have 10+ years in ASIC verification, strong SystemVerilog/UVM skills, and familiarity with formal methods or assertions.

Qualifications

• Minimum 10 years of experience with a BS or 8 years with a MS in CS/EE/CE or related field.
• Expertise in SystemVerilog, UVM/OVM/VMM, and verification methodologies.
• Experience with SVA/PSL/OVL assertions and coverage-driven verification.

Responsibilities

• Design and implement verification test benches for system, chip and block levels.
• Develop functional test plans and coverage methodologies.
• Collaborate with VLSI Design team to implement verification strategies.
• Lead or assist in project/team leadership as needed.

Skills

SystemVerilog

UVM/OVM/VMM

Verification test benches

Coverage verification

Assertions (SVA/PSL/OVL)

Communication skills

Education

BS in CS/EE/CE or related field

MS preferred

Tools

Cadence IFV

Jasper

Job description

Jariet Technologies, Inc., a CesiumAstro subsidiary, is seeking a Principal ASIC Functional Verification Engineer to shape verification strategies for high-speed SoCs. You will craft advanced test benches, apply UVM/OVM/VMM, and partner with the VLSI design team to ensure robust coverage and correctness in digital communications silicon.

Ideal candidates have 10+ years in ASIC verification, strong SystemVerilog/UVM skills, and familiarity with formal methods or assertions.