Senior ASIC Design Lead for High-Speed DSP & RF Chips

Cesiumastro; Aliso Viejo (CA); On-site; USD 15,000 - 199,000; Full time

Benefits offered by this job

Stock options

Health benefits (dental, vision)

HSA/FSA programs

Retirement plans

Job summary

CesiumAstro is seeking a Principal ASIC Design Engineer – Chip Lead in its Jariet Technologies group in California. You will drive cradle-to-grave high-speed mixed-signal/DSP chip projects, from architecture through production.

The role demands deep RTL/SystemVerilog expertise, verification using UVM/VMM/SPECMAN, and collaboration with frontend/backend teams to meet demanding performance, power, and timing goals. A Master’s degree and 10+ years' experience are required.

Qualifications

• Master’s in Engineering with 10+ years of experience.
• Experience in IC/ASIC development flow from concept through silicon release.
• System simulation to RTL, verification, synthesis, and backend interfacing.
• High-speed analog block integration into digital logic.
• Ability to analyze specs at architecture/micro-architecture levels.
• Excellent program management and project tracking skills.
• Experience with customer communications and marketing interactions.
• ASIC verification experience using UVM, VMM, OVM or SPECMAN.
• Fluency with Verilog/SystemVerilog; synthesis/STA; low-power design desirable.
• DSP block implementation desirable.

Responsibilities

• Lead cradle-to-grave ASIC/Chip design programs for high-speed mixed-signal DSP.
• Collaborate with frontend/backend teams to move silicon from concept to production.
• Engage with customers and cross-functional teams to define requirements.

Skills

IC/ASIC development flow

RTL design

High-speed DSP

UVM/VMM/SPECMAN verification

Synthesis & STA

Low power design

Project management

Customer communications

Education

Master’s in Engineering

Tools

UVM

VMM

SPECMAN

Job description

CesiumAstro is seeking a Principal ASIC Design Engineer – Chip Lead in its Jariet Technologies group in California. You will drive cradle-to-grave high-speed mixed-signal/DSP chip projects, from architecture through production.

The role demands deep RTL/SystemVerilog expertise, verification using UVM/VMM/SPECMAN, and collaboration with frontend/backend teams to meet demanding performance, power, and timing goals. A Master’s degree and 10+ years' experience are required.