Senior ASIC Design Engineer - Video IP RTL Architect

Trilinear Technologies; Portland (OR); Presencial; USD 90.000 - 130.000; Jornada completa

Descripción de la vacante

Trilinear Technologies in Portland, OR is seeking an experienced RTL engineer to contribute to the next generation of IP products. You will develop high-quality RTL and SystemVerilog code while collaborating with customers to integrate our designs into their architectures.

The ideal candidate will have 5+ years in RTL development, strong Verilog/SystemVerilog experience, and a proven track record of delivering reliable IP.

Formación

• 5 years of industry experience in RTL development.
• Experience with Verilog or SystemVerilog in complex IP and SOC design.
• Proven track record of delivering high quality designs.
• Block level and system level verification using bus functional models and/or verification IP.
• Mentor, Cadence or Synopsys simulation tools.
• Proven ability to work in a small company environment.

Responsabilidades

• Contribute to the design and development of the next generation of IP products.
• Develop innovative micro-architectures.
• Deliver high-quality RTL code using SystemVerilog.
• Work with customers to successfully integrate our products into their designs.

Conocimientos

RTL development

SystemVerilog

Herramientas

Verilog

SystemVerilog

Mentor/Cadence/Synopsys tools

Descripción del empleo

Trilinear Technologies in Portland, OR is seeking an experienced RTL engineer to contribute to the next generation of IP products. You will develop high-quality RTL and SystemVerilog code while collaborating with customers to integrate our designs into their architectures.

The ideal candidate will have 5+ years in RTL development, strong Verilog/SystemVerilog experience, and a proven track record of delivering reliable IP.