ASIC RTL & SoC Design Engineer – Video/Image Processing

The Richmond Group USA; San Jose (CA); On-site; USD 171,000 - 209,000; Full time

Benefits offered by this job

Stock options

Annual bonus

Work-life balance

Job summary

The Richmond Group USA partnering with a leading semiconductor company seeks an ASIC Design Engineer RTL and SoC for its San Jose R&D team. This hands-on role covers video and image-processing ICs across microarchitecture, RTL design, SoC integration, verification, tape-out, and chip bring-up.

You will join a stable, long-tenured engineering group with ownership across the full chip-development lifecycle, in a Bay Area market that values long-term viability.

Qualifications

• Bachelor’s degree in Electrical Engineering or EECS; master’s preferred.
• Minimum three years in VLSI/ASIC/RTL or digital IC design.
• Experience with Verilog or SystemVerilog and complex-block microarchitecture.
• Familiarity with verification planning, coverage, and multi-clock-domain designs.
• Knowledge of image processing or signal processing.
• Exposure to scripting, synthesis, static timing analysis, DFT, or ATPG.
• Strong execution, attention to detail, and ability to work independently and collaboratively.

Responsibilities

• Develop complex ASICs for video-surveillance and automotive applications.
• Own microarchitecture definition, RTL design, integration, and verification.
• Develop test plans and support block-level and whole-chip validation.
• Work with multi-clock-domain designs, synthesis, timing closure, DFT, and ATPG.
• Collaborate with test, production, firmware, and other engineering teams.
• Contribute across the complete chip-development lifecycle.

Skills

VLSI/ASIC/digital IC design

Verilog/SystemVerilog

Multi-clock-domain design

Verification planning/coverage

Image processing/Signal processing

Scripting (Python)

DFT/ATPG

Education

Bachelor’s degree in Electrical Engineering/EECS

Master’s degree preferred

Tools

Synthesis

Static timing analysis

DFT/ATPG tools

Scripting languages (Python, Tcl)

Job description

The Richmond Group USA partnering with a leading semiconductor company seeks an ASIC Design Engineer RTL and SoC for its San Jose R&D team. This hands-on role covers video and image-processing ICs across microarchitecture, RTL design, SoC integration, verification, tape-out, and chip bring-up.

You will join a stable, long-tenured engineering group with ownership across the full chip-development lifecycle, in a Bay Area market that values long-term viability.