Senior ASIC Design Engineer

Trilinear Technologies; Portland (OR); On-site; USD 90,000 - 130,000; Full time

Job summary

Trilinear Technologies in Portland, OR is seeking an experienced RTL engineer to contribute to the next generation of IP products. You will develop high-quality RTL and SystemVerilog code while collaborating with customers to integrate our designs into their architectures.

The ideal candidate will have 5+ years in RTL development, strong Verilog/SystemVerilog experience, and a proven track record of delivering reliable IP.

Qualifications

• 5 years of industry experience in RTL development.
• Experience with Verilog or SystemVerilog in complex IP and SOC design.
• Proven track record of delivering high quality designs.
• Block level and system level verification using bus functional models and/or verification IP.
• Mentor, Cadence or Synopsys simulation tools.
• Proven ability to work in a small company environment.

Responsibilities

• Contribute to the design and development of the next generation of IP products.
• Develop innovative micro-architectures.
• Deliver high-quality RTL code using SystemVerilog.
• Work with customers to successfully integrate our products into their designs.

Skills

RTL development

SystemVerilog

Tools

Verilog

SystemVerilog

Mentor/Cadence/Synopsys tools

Job description

Who We Are:

Trilinear Technologies is a unique organization that offers premium intellectual property cores and design services from a team of highly experienced video and image processing engineers.Our work can be found in applications ranging from automotive displays to cloud servers to VR head sets.With deep expertise in delivering high quality video systems, Trilinear provides ASIC, FPGA and software solutions to solve complicated customer design challenges.

Who We Want:

The ideal candidate will be creative and highly motivated.They will know the difference between getting a job done and getting a job done properly.Knowing the tools and how to code is not enough.The right candidate will understand that quality matters in everything that they produce.The candidate will be a creator and not an integrator.They must understand how to deliver professional quality code on a predictable schedule.

Job Responsibilities:

• Contribute to the design and development of the next generation of IP products.


• Develop innovative micro-architectures


• Deliver high-quality RTL code using SystemVerilog


• Work with customers to successfully integrate our products into their designs.

Job Requirements:

• 5 years of industry experience in RTL development, please no students for this role.


• Experience with Verilog or System-Verilog in complex IP and SOC design.


• Proven track record of delivering high quality designs.


• Block level and system level verification experience using bus functional models and/or verification IP.


• Mentor, Cadence or Synopsys simulation tools.


• Proven ability to work in a small company environment

Preferred Experience:

• Successful tape out experience


• Experience with linting tools, CDC and formal verification.


• Deep knowledge of video and image processing systems


• Experience with high speed SerDES interfaces


• Good knowledge of video and image compression algorithms