Senior ASIC Design Engineer - NoC & High-Perf Interfaces

Anysilicon; Santa Clara (CA); Hybrid; USD 170,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking an ASIC design engineer to contribute to high‑performance network chips and NoC integration.

You will collaborate with architecture, IP, physical design, and product teams to drive first‑pass silicon success for AINIC and DPU projects. The role involves designing and verifying AXI, ACE, and APB interfaces, managing queueing and buffer resources, and providing post‑silicon bring-up support.

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• Understanding of Network-on-Chip (NoC) architecture and protocols.
• Experience with AXI, ACE, and APB interface design and verification.
• Knowledge of queuing system design and buffer management.

Responsibilities

• Contribute to ASIC design for high-performance network chips: AINIC and DPU.
• Work within the NTSG ASIC Design Team to develop cutting-edge designs.
• Collaborate with architecture, IP design, physical design teams, and product engineers to ensure first-pass silicon success.
• Engage in Network-on-Chip (NoC) design and integration.
• Design and verify AXI, ACE, and APB interfaces.
• Provide post-silicon bring-up support and yield learning.

Skills

VCS simulation tools

Scripting (Perl/Python/Shell)

SystemVerilog/Verilog RTL

NoC/Network protocols

Education

Bachelor's or Master's degree in Computer/Electrical Engineering

Tools

Verilog/VCS

Job description

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking an ASIC design engineer to contribute to high‑performance network chips and NoC integration.

You will collaborate with architecture, IP, physical design, and product teams to drive first‑pass silicon success for AINIC and DPU projects. The role involves designing and verifying AXI, ACE, and APB interfaces, managing queueing and buffer resources, and providing post‑silicon bring-up support.