SR ASIC Design Engineer – Ethernet Switch & High-Speed I/O

Anysilicon; Santa Clara (CA); Hybrid; USD 170,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc in Santa Clara, CA is seeking an SR ASIC Design Engineer for Ethernet Switch & High-Speed I/O. You will contribute to ASIC design for high-performance network chips and collaborate with architecture, IP, and physical design teams to ensure first-pass silicon success.

The role covers front-end RTL design, Ethernet subsystem integration, switch fabric and buffer/queue systems, and post-silicon yield learning.

Qualifications

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• Knowledge of Ethernet protocols and switch design.
• Experience with high-speed I/O (SerDes) architectures and verification.

Responsibilities

• Contribute to ASIC design for high-performance network chips, specifically AINIC and DPU.
• Engage in Ethernet subsystem design and integration.
• Design and implement switch fabric, buffer, and queue systems.
• Front-end RTL design and integration of high-speed I/O subsystems.
• Collaborate with architecture, IP, and physical design teams for silicon success.
• Support post-silicon bring-up and yield learning.

Skills

Ethernet protocols

Switch design

Buffer/Queue management

SerDes / high-speed I/O

Scripting (Python/Perl/Shell)

SystemVerilog/Verilog RTL design

Education

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Tools

VCS

Verilog/SystemVerilog RTL

Job description

SR ASIC Design Engineer – Ethernet Switch & High-Speed I/O

Advanced Micro Devices, Inc, 2485 Augustine Drive, Santa Clara, CA 95054

Job Description:

At AMD, we are dedicated to building innovative products that enhance next-generation computing experiences across various domains, including AI, data centers, PCs, gaming, and embedded systems. Our culture emphasizes collaboration, bold ideas, and a commitment to excellence, making us a leader in addressing the world's most pressing challenges. Join us to shape the future of AI and advance your career in a dynamic environment.

Responsibilities:

• Contribute to ASIC design for high-performance network chips, specifically AINIC and DPU.
• Engage in Ethernet subsystem design and integration.
• Design and implement switch fabric, buffer, and queue systems.
• Perform front-end RTL design and integration of high-speed I/O subsystems.
• Collaborate with architecture, IP, and physical design teams to ensure first-pass silicon success.
• Support post-silicon bring-up and yield learning.

Qualifications:

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Skills:

• Knowledge of Ethernet protocols, switch design, and buffer/queue management.
• Understanding of high-speed I/O (SerDes) architecture, design, and verification.
• Experience with VCS simulation tools, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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