Senior ASIC Design Engineer — AI Driven High-Perf SoCs

Palo Alto Networks; United States; On-site; USD 156,000 - 253,000; Full time

Job summary

Palo Alto Networks is seeking an experienced lead ASIC designer to own front-end design from spec to silicon bring-up for next-generation firewall platforms. You will develop SystemVerilog RTL and drive design verifications spanning simulation, emulation, and silicon bring-up.

Collaborating with verification and physical-design teams, you will review timing, optimize power and area, and explore AI-driven flows to mitigate schedule risk while delivering high-performance, low-power cores.

Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
• 10+ years' front-end ASIC design ownership, shipping 2+ chips to mass production.
• Expert SystemVerilog RTL skills.
• Proven track record of selecting, integrating, and configuring IP blocks for PCIe, Ethernet, or DDR.
• Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
• Defining micro-architecture from high-level requirements.
• Datapath design for intricate synch/asynch digital logic.
• Debugging across simulation, emulation, and silicon.
• Analyzing timing, power, and area reports and driving fixes.
• Excellent leadership, collaboration, and written/verbal communication.

Responsibilities

• Own module design from specification through silicon bring-up.
• Write clear design and micro-architecture specifications.
• Design SystemVerilog RTL that meets area, performance, and power targets.
• Verify blocks with simulation, emulation, formal methods, and silicon bring-up.
• Collaborate with verification engineers to debug scenarios and close coverage.
• Partner with physical-design teams to review reports and optimize timing.
• Innovate with AI-driven design or verification flows to reduce schedule risk.

Skills

SystemVerilog RTL

Scripting (Python, C/C++, Perl, Bash)

Front-end ASIC design ownership

PCIe/Ethernet/DDR interfaces

Debugging (sim/emulation/silicon)

Datapath design

Leadership & collaboration

Education

BS in EE, CE, or CS

MSEE or equivalent military experience

Job description

Palo Alto Networks is seeking an experienced lead ASIC designer to own front-end design from spec to silicon bring-up for next-generation firewall platforms. You will develop SystemVerilog RTL and drive design verifications spanning simulation, emulation, and silicon bring-up.

Collaborating with verification and physical-design teams, you will review timing, optimize power and area, and explore AI-driven flows to mitigate schedule risk while delivering high-performance, low-power cores.