SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O

AMD; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a highly skilled ASIC front-end design engineer to contribute to the design of high-performance network chips (AINIC and DPU). You will collaborate with architecture, IP design, and physical design teams to achieve first-pass silicon success in a fast-paced environment at our Santa Clara location.

The ideal candidate will have a strong background in RTL design, Verilog, and verification, with experience across Ethernet protocols, SerDes architecture, and related tools.

Qualifications

• Bachelor's or Master's degree in computer engineering or electrical engineering.
• Prior experience in ASIC front-end design or RTL development is preferred.
• Strong communication and problem-solving skills are desirable.

Responsibilities

• Ethernet subsystem design and integration.
• Switch fabric, buffer, and queue design and implementation.
• Front-end RTL design and integration of high-speed I/O subsystems.
• Collaborate with architecture, IP, and physical design teams for first-pass silicon success.
• Post-silicon bring-up support and yield learning.

Skills

Ethernet protocols

SerDes high-speed I/O

SystemVerilog/Verilog RTL design

Education

Bachelor's or Master's in Computer/ Electrical Engineering

Tools

VCS

Perl/Python/Shell scripting

Job description

Overview

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

The Role

You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and DPU. As a member of the NTSG ASIC Design Team, you will help bring to life cutting‑edge designs. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail‑oriented, possessing good communication and problem‑solving skills.

Key Responsibilities

• Ethernet subsystem design and integration
• Switch fabric, buffer, and queue design and implementation
• Front‑end RTL design and integration of high‑speed I/O subsystems
• Collaboration with architecture, IP, and physical design teams for first‑pass silicon success
• Post‑silicon bring‑up support and yield learning

Preferred Experience

• Knowledge of Ethernet protocols, switch design, and buffer/queue management
• Understanding of high‑speed I/O (SerDes) architecture, design, and verification
• Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Location

Santa Clara, CA

Additional Information

This role is not eligible for visa sponsorship.

Equal Opportunity Statement

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AI Use Disclaimer

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.